The present invention relates to a method and apparatus of scanning control for information processing systems.
An effective method of maintenance and diagnosis for information processing systems which has widely been employed conventionally is the scan-in/scan-out control system. Scanning is defined to be a special data storage access operation, in which data storage elements, such as registers, flip-flops and memory devices in the processing system, are given specific addresses (scanning addresses) in advance and these storage elements are addressed for writing in predetermined values (scan-in) or reading out the contents (scan-out) in accordance with scanning logic independently of the normal logic operation.
This technique is applied, for example, to micro-diagnosis in which a diagnosis controller carries out scan-in and scan-out for a storage element and compares read-out data with the reference value so as to diagnose the logical operation of the element, and to a logging operation in which the states of registers, flip-flops and memory devices at the time of failure are read out to an external memory unit for analyzing the failure.
Due to a large number of logic circuits integrated within a chip, which has been achieved by recent advances in semiconductor technology, it is difficult to observe individual logic signals from outside using a logic scope and the like, and therefore, the scanning operation which can directly access logic circuits has become a desirable ojective.
In the conventional scanning system, a scanning address is assigned to each data storage element such that logically related flip-flops are provided with a common scanning address and word registers related closely in a logical sense are provided with consecutive addresses for the convenience of hardware and software using the scanning operation.
However, in many cases, such logical conditions do not match the packaging conditions of, for example, LSI chips and package boards. Namely, logical assignment of the scanning address invites the need for additional logic gates. In some extreme cases, logical assignment of the scanning address is degraded to a split address assignment, that tends to increase the complexity of the diagnosis controller. In addition, a change in the logical design directly affects the assignment of the scanning address, and frequent alterations of the scanning address result in an increased manpower in designing hardware and software systems.